10/4 整體講解(上)

(1) module top;
     system clock #200 clock(A); 註:修改period 為200週期
     system clock # 100 clock(B);
     system clock # 50 clock(SEL);
     mux m1 (OUT,SEL,A,B);
     endmodule
(2)模組 modules
     module mux (OUT,SEL,A,B);
     . . . . . . .
     endmoule
(3)moule system clock(clk);
    parameter period = 100;
    output clk;
    reg clk ;
    initial clk = 0 ;
    always begin           註 :無窮迴圈
    #(period/2)clk =~clk 註:延遲  註:反向
    end
    always @ (posedge clk)     註:@當clk   註:正緣
    if ($ time >1000)                註:做到1000奈秒    
       $ stop ;
    endmodule